1. Field of the Invention
This invention relates to a 3-dimensional integrated circuit designing method of layout for stacking and arranging integrated circuits. Further, this invention relates to a 3-dimensional integrated circuit formed by use of the above method and to a computer readable medium encoded with a computer program to perform the above method.
2. Description of the Related Art
Recently, with the miniaturization of CMOS devices, a delay associated with interconnects becomes relatively longer in comparison with a delay caused by transistors themselves. Therefore, the delay associated with interconnects becomes a factor dominating the performance of the integrated circuit. For example, in an example of a CMOS inverter, if the inverter is further miniaturized, a delay associated with interconnects becomes longer than a delay caused by the inverter. In order to reduce the delay associated with interconnects, it is necessary to reduce the number of long interconnects. As will be described later, according to experiments performed by the inventor of this application and others, it is understood that it is necessary to reduce the number of interconnects whose lengths are larger than 100 μm. As a method for reducing the number of interconnects that are long, it is said that it is desirable to use a method for stacking circuits in a 3-dimensional fashion.
However, even if a 3-dimensional stacking technique is used, a sufficient effect cannot be attained when a simple layout is made. For example, in an integrated circuit chip having one side of 10 mm, the maximum length of the interconnect becomes approximately 20 mm. In a case where four portions obtained by equally dividing the chip are stacked, it is understood that the number of interconnects whose lengths are larger than 100 μm is almost unchanged when the distribution of interconnect lengths of the integrated circuit is derived by calculation. That is, the effect that the delay associated with interconnects is reduced cannot be substantially attained simply if the circuits are stacked into four layers.
In order to reduce the number of interconnects whose lengths are larger than 100 μm, the number of stacked layers must be extremely increased. For example, if the chip is divided into 100 portions and the divided portions are stacked, the length of the interconnect becomes approximately 200 μm at maximum, and as a result, interconnects whose lengths are larger than 100 μm are mostly eliminated. However, as the number of stacked layers becomes larger, heat conductance is lowered and the cost for the stacking process becomes higher. For this reason, it is considered that an adequate number of stacked layers is approximately 10 or less. Therefore, it is desired to provide a layout method capable of reducing the number of interconnects whose lengths exceed 100 μm even if the number of stacked layers is set to approximately 10 or less.
In order to solve the above problem, a method for folding and making the layout of a 2-dimensional integrated circuit as is used in the art of folding origami paper is proposed (JP-A 2007-250754 (KOKAI) or J. Cong, G. Luo, J. Wei, and Y. Zhang, “Thermal-Aware 3D IC Placement via Transformation,” Proceedings of the 12th Asia and South Pacific Design Automation Conference (ASP-DAC 2007), Yokohama, Japan, pp. 780-785, January 2007). However, even if the above methods are used, the interconnect length can be reduced only to the length of one side obtained after folding. That is, basically, the above problem cannot be solved. In other words, the interconnect length cannot be sufficiently reduced if the number of stacked layers is set to an extremely large number.